This invention relates to methods for testing electrical devices, and more particularly to a testing arrangement for printed circuit boards or the like.
Electrical components such as printed (or etched) circuit boards must be tested after manufacture has been completed. The testing is primarily directed to determining whether or not all of the conductive paths are in their designated positions and no conductors are unintentionally shorted, and whether electrical continuity exists where it should. Various functional tests may be executed using the external connectors (those included for operation in the end equipment), and also visual inspection can provide an indication of the quality of the part. Such methods can be time-consuming and expensive, however, and in any event are not always effective in discovering shorts or opens which may be hidden from view or not exercised in the electrical functional tests chosen. For these reasons, various other test mechanisms have been proposed which perform the function of scanning the surface of a etched circuit board and providing an indication of the wiring integrity.
One example of prior testing methods used electron beam technology to scan an integrated circuit chip or an etched circuit board under test while detecting secondary electrons emitted by the pattern on the board. One of these methods is referred to as a Voltage Contrast Electron Beam (VCEB) technique; these testers are like logic analyzers which probe functional electronic circuits on semiconductor integrated circuit chips. The VCEB technique is described by Woodard et al, J. Vac. Sci. Technol., November/December 1988, p. 1966, "Voltage Contrast Electron Beam Testing Experiments on Very Large Scale Integrated Circuit Chip Packaging Substrates". When used for testing relatively large devices such as printed wiring boards, the VCEB technique requires complex and expensive electron beam generating and deflecting arrangements, as well as requiring a large evacuated chamber.
In copending application Ser. No. 424,396, filed Oct. 20, 1989 by Richard I. Mellitz for Electro-emissive Laser Stimulated Test, assigned to Digital Equipment Corporation, a testing method is described which uses a laser beam to scan an electro-emissive grid positioned over the board under test, and the grid emits electrons to charge nodes on the board; this charging can be detected to check the integrity of the conductor paths on the board. While this method avoids the difficulties of handling an E-beam, and is thus much less expensive, there is nevertheless still the necessity for an evacuated chamber, and other expensive components.
In U.S. Pat. No. 4,565,966 a method for testing circuit boards is disclosed which uses two probes for making resistive or RF impedance measurements to verify the integrity of the boards. This method, however, requires two probes, each with their attendant X-Y-Z positioning mechanisms, and a capacitance data file.
In U.S. Pat. No. 4,229,693 a single-probe capacitance measurement method is described, used in testing of printed circuit boards. A probe is used to make contact to the conductors of the board to measure the capacitance to thereby detect open circuit and short circuit networks on the board. This technique, however, does not provide any facility for measuring any previous electrical states of the network being probed. Thus, when two or more networks have been identified as open or shorted, they must be located and verified with two probes using a resistance type of measurement. Further, this method requires that the capacitance values of each network be known. In order to acquire this data, a known good module must be available to obtain the capacitance values since they cannot easily be calculated, or a group of unknown modules may be used and the results analyzed to obtain the values. Commercial equipment available using this type of testing method includes a Teledyne TAC capacitance probing system.